The invention of solid state transistor by Shockley, Bardeen and Brattain at bell laboratories can be thought of as the greatest invention of the 20th century as it brought about the information age with the transistor being at the center stage 1). In the 1950s most research and engineering on semiconductors was directed to germanium with Japan leading in civilian application research and the United States of America leading the research in military and space exploration applications. In the 1960s the development of the planner technology resulted in the replacement of germanium devices with silicon semiconductor devices. 2).

In 1965 Gordon E. Moore postulated a law that; the number of the number of transistors in a dense integrated circuit doubles every two years 8). The size of the transistor has reduced to the extent that quantum tunneling has became a challenge and now most of research is being focused on increasing device speed other than size reduction. Amorphous silicon (a-Si) has been used in the backplane (TFT plane) in large area display with mobility of  0.5cm2V-1s-1 3). In backplane of small and medium display, polycrystalline silicon has had wide industrial application with mobility  100cm2V-1s-1 4). In flexible display so far a mobility of 20cm2V-1s-1 has found commercial application using the OLED (Organic Light Emitting Diode) display 5). For high resolution, high refresh rate and optimal fill factor a higher mobility is desirable. This can be achieved by use of other materials such as germanium that has higher electrons and holes densities as well as smaller band gap when compared to silicon 3, 4). There is also need for lowering of the process temperature to make it possible for realization of wearable electronics, high resolution flexible display and sheet computer in which the substrate materials would decompose if subjected to the process temperature of the former material 4).

Ge has been studied to a great extent as the next active semiconductor material for MOSFET (Metal Oxide Semiconductor Field effect Transistor) devices. P.H. Park et al. successfully applied metal-induced crystallization (MIC) on Ge using pure gold as a catalyst and realized a p-type crystalline Ge film with large crystal grains over 50μm and hole mobility as high as 160cm2V-1s-1 after annealing Au/Ge bi-layer at 250˚C for 150 hrs 6). T. Sugiyama et al. have successfully fabricated crystalline Ge film by co-deposition of Au and Ge at low substrate temperatures (<200˚C) without post annealing. They reported a film with grain sizes of ~ 100nm 7); however polycrystalline Ge is highly p-type a scenario attributed to defects such as vacancies, dislocations and stacking faults 5). R. Yoshimine et al investigated the effect of interlayer on silver-induced layer exchange crystallization of amorphous germanium thin film on insulator and achieved crystalline Ge of smaller grain size in comparison to Al or Au induced crystallization 9). Fabrication of n-type Ge FET, the polycrystalline Ge has to be doped with some donor impurities and this will pave way for the realization of Ge Complementary p-channel and n-channel MOSFET pair (CMOS) device which has low power consumption and good noise immunity 4). T. Suzuki et al. demonstrated how crystallization and donor activation of Ge thin films can be achieved at the same time by AgSb induced layer exchange at temperature as low as 330˚C 4). In this study the effect of varying the Sb concentration in layer exchange MIC using AgSb alloy as a catalyst is elucidated.

AgSb thin films (20nm) were deposited by thermal vacuum evaporation of commercially available 99wt%Ag1wt%Sb (Good fellow Cambridge) that was diluted with pure silver to achieve Sb concentration variation at 1wt%, 0.5wt%, 0.25wt%, 0.1wt% and 0wt% on to a highly doped n-type Si wafer with 100nm of thermally oxidized layer that acted as the gate insulation. Subsequently, 60nm of a-Ge was sputter-deposited on to the AgSb films in a radio frequency direct current sputtering system. The samples were annealed in N2 gas ambience at temperature 603.15K for one hour with a rise gradient of 80K per minute from room temperature (RT) and free cooling to RT. The samples were the characterized by X-ray diffraction (XRD), Raman spectroscopy and secondary ion mass spectrometry (SIMS). The samples were then etched in nitric acid to selectively remove the Ag film. With appropriate mask Ti was sputter deposited on to the samples to make the source and drain electrodes and complete the TFT fabrication.The highly doped n-Si and the thermally formed 100nm SiO2 were used as gate electrode and gate insulation, respectively.

Fig. 1 show XRD profiles of the samples with Ge oriented in the (111) plane being observed in all the samples. This result signifies that there was no dependence of peak position as a function of Sb concentration variation. Fig. 2 (a) shows Raman spectra of samples and a pure Ge wafer spectra for reference.  Fig. 2 (b) shows the full width at half maximum (FWHM) for the samples was more than twice that of pure Ge crystal at 3 wave number cm-1 implying poor crystallinity.  In materials design there has to be a trade-off between crystallinity and electrical properties thus the poor crystallinity was inevitable in achieving n-type Ge thin films. Fig. 2 (c) show the peak positions were shifted to the left when compared to that of pure Ge at 300 wave number cm-1, this shift signified presence of compressive strain in the films that can be attributed to difference in coefficients of thermal expansion/ contraction between SiO2, Ge and Ag. This strain can also be attributed to lattice mismatch between the substrate and the Ge film. Fig. 3 shows the secondary ion mass spectrometry (SIMS) depth profile of the grown Ge thin films. It is observed that the Sb atoms concentration in the samples with 1wt%Sb was 1×1020 atoms cm-3 while that grown 0.5wt%Sb was 8×1019 atoms cm-3, that grown with 0.25wt%Sb was 2×1019 atoms cm-3 and that grown with 0.1wt%Sb was less then 2×1019 atoms cm-3. This is in conformity with calculated expected concentration assuming 1022 atoms cm-3.

Fig. 1 XRD pattern for Ge thin films AgSb with varied concentration of Sb.

Fig. 2 (a) Raman spectra of the Ge thin films (b) FWHM of the Raman spectra of the samples (c) peak position of the spectra.

Fig. 3 SIMS depth profile of Sb concentration for samples grown with Sb wt% of 1, 0.5, 0.25 and 0.1 annealed for 1hr at 603.15K and chemically etched.

The IdVd characteristics of the samples Fig. 4 (a) – (e) showed that film grown with 0.25wt% Sb had ambipolar behavior, films grown with concentration above 0.25wt% Sb had n-type behavior and films grown with concentration below 0.25wt% had p-type behavior. This result showed that the transition between n-type and p-type behavior occurs at 0.25wt% concentration.  The electron mobility in the sample grown with 0.5wt%Sb and that grown with 1wt%Sb was calculated as 2.13 cm2V-1s-1 and 0.519cm2V-1s-1, respectively while the carrier densities were evaluated at 1.64 x1017 cm-3 and 1.7 x 1017 cm-3, respectively. When the electrons carrier density is compared to the results obtained in SIMS measurements it can be deduced that not all the Sb atoms in the Ge lattice are ionized.   The holes mobility in the sample grown without Sb and that grown with 0.1wt%Sb was calculated as 3.72 cm2V-1s-1 and 1.13cm2V-1s-1, respectively while the carrier densities were evaluated at 1.21 x1017 cm-3 and 1.35 x 1017 cm-3, respectively.  The p-type behavior originates from defects such as vacancies, dislocations and stacking.

In conclusion it has been showed that to achieve n-type Ge thin films by metal-induced crystallization the Sb concentration in the catalyst AgSb alloy should be greater than 0.25wt%. The process needs more improvement to achieve higher electrons mobility, achievement of donor activation at low temperature close to the process temperature of flexible material polyimide (PI) is a step in the right direction to realization of CMOS devices on flexible substrate.

References

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  • Sugiyama, N. Mishiba, M. Kamiko and K. Kyuno. Fabrication of crystalline Ge thin films by co-deposition of Au and Ge at low substrate temperature (<200˚C) without post annealing, 2016 Appl. Phys. Express. 9, 095501(2016).
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  • Yoshimine, K. Toko and T. Suemasu, Effect of interlayer on silver-induced layer exchange crystallization of amorphous germanium thin film on insulator, Japanese Journal of Applied Physics 56, 05DE04.

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